Binary floating point numbers such as those defined in the Institute of Electrical and Electronic Engineers (IEEE) standard 754 are capable of representing floating point numbers which can be operated on quickly and simply within a binary computer. A generalised example of an IEEE 754 standard floating point number is +(X.Y)*(2n). The floating point number has three basic components, the sign, the exponent, and the mantissa.
In the generalised form shown above the ‘+’ part is represented by the sign component, the ‘X.Y’ part by the mantissa, and the ‘2n’ component by the exponent.
The mantissa is composed of the fraction, representing the ‘Y’ part, and an implicit leading digit representing the ‘X’ part. The implicit leading digit is a ‘1’ when the floating point is a normalised number, and a ‘0’ when the floating point is a denormalised number. A number is normalised when the exponent part of the number is greater than its smallest number.
The exponent is required to represent both positive and negative numbers. In order to do this a bias value is added to the actual exponent value in order to get the stored exponent. Furthermore the exponent values of −127 (all 0's) and +128 (all 1's) are reserved for special numbers.
As is known in the art a single precision or 32 bit floating point number according to the IEEE standard has 1 bit allocated for the sign part, 8 bits allocated to the exponent, and 23 bits allocated to the fraction. However double precision or 64 bit floating point numbers are similarly known, whereby 1 bit is allocated to the sign part, 11 bits allocated to the exponent, and 52 bits allocated to the fraction.
Therefore the smallest normalised number for a single precision number is 2−126 and for a double precision number is 2−1022.
Floating point multiplication circuitry is also known in the art. FIG. 1 shows a schematic view of a known single precision floating point multiplier circuit 1 capable of multiplying floating point numbers FA and FB. The numbers FA and FB are also known as operands. FIG. 1 shows that in order to carry out a floating point multiplication the multiplier circuitry 1 is divided into five circuit elements, explained below.
A comparator 2 compares sign bits S_FA, S_FB to determine if the output value is a positive or negative number. This is carried out in FIG. 1 by the XNOR gate.
An integer multiplier 3 multiplies the operand mantissas M_FA and M_FB to produce a mantissa product M_FC.
An adder stage 5, 7 adds the operand exponents E_FA and E_FB, with an additional offsetting to compensate for the original offset of E_FA and E_FB, to produce an exponent sum E_FC.
A post multiplication normaliser 9 normalises the mantissa product to bring the mantissa back into the form 1.Y, i.e. with an implicit leading value of 1. The normalisation may require the exponent sum E_FC to be modified.
Finally a rounding circuit 11 rounds the normalised mantissa product, to reduce the number of bits used to represent the number and therefore enable the product to be represented by the same number format as the operands.
In a typical digital signal processing circuit or general purpose processor it is typical to save space by using the same integer multiplier for the multiplication of operand floating point mantissas and for standard integer multiplication. For example multiplication using a 32 bit or single precision floating point number would typically use the same multiplier block as a double or 32 bit integer multiplication.
A typical integer multiplier comprises an operand encoder, a partial product generator, a product term compressor or combiner, and a final term addition stage. The operand encoder encodes the first operand and reduces the number of terms representing the operand. The partial product generator multiplies the second operand by each of the encoded terms to produce partial product terms. The product term compressor adds together (or as otherwise known compresses) the many partial products to form a pair of terms. Finally the addition stage adds the pair of terms together to form the final value.
The product term compressor is carried out by a series of compression stages, each of which comprise compression circuit cells. Examples of compression circuit cells are half-adders, full-adders and 4:2 compressors, which receive a number of inputs and output a sum with fewer outputs.
Compression stages have been typically designed to optimise the reduction of all of the possible partial products terms generated by the full width of the operand to form two terms within the smallest number of consecutive stages.
As the speed of the processing is fixed by the number of compression stages a floating point mantissa multiplication takes the same amount of time as an integer calculation. This results in a floating point multiplication taking a much greater amount of time to complete than a integer multiplication due to the additional processes required to produce a complete result such as those described above.